As in all microcontrollers watchdog timers purpose isto reset microcontroller after reasonable amount of MCU error time. If watchdog is enabled and if after some time watchdog timer doesn't reload due correct program flow, then it generates a system reset. Watchdog unit consists of four registers: WDMOD – Watchdog mode register where is watchdog mode and status saved. There are three watchdog modes available in LPC2000: Debug mode – allows to debug code with watchdog active but without WD reset; Watchdog Interrupt mode – generates interrupt when WD timer overflows; Watchdog Reset mode – reset MCU when WD timer overflows. WDTC – Watchdog timer constant register where time out value is saved. Timeout value can be determined by formula: Period=Pclk·WDTC·4. While WDTC value can be in range from 256 to 2^32, then timeout when Pclk=60MHz can vary from 17.066us to 5min. WDFEED – watchdog feed sequence register. Writing 0xAA followed by 0x55 wil reset Watchdog to WDTC value. WDTV – watchdog timer value register holds current watchdog timer value which can be read. When started watchdog timer must get regular feed sequence in order to avoid reaching zero and reset.
In ARM7 microcontrollers PWM is designed as separate module but it has all features as a general purpose timers have, just limited pins are associated. PWM module have improved match module which allows to have six channels of single edge controlled PWM or three double edge controlled PWM. There are seven match registers used with improved update logic. PWM modulator have additional shadow match registers that perform latch effect. This means that you can update match registers on instantly, but new values are taking effect only at the beginning of new cycle. This mechanism ensures that all updates are performed at he beginning of a new cycle through latch enable register(LER). In general purpose timers match registers take effect immediately after they are updated.
LPC2000 microcontrollers have at least two 32 bit timer counters. Lets take LPC2148 microcontroller where are two general purpose 32 bit timers that are identical except peripheral base address. These timers are for general purpose that can perform timer and counter operations. Timers have many features: Programmable 32 bit pre-scaler; Up to four 32 bit capture channels that can take snapshots with interrupt generation ability; Four 32 bit match registers that allow generate interrupt on match, generate interrupt and stop timer, generate interrupt and reset timer; Up to four output pins that can be set LOW/HIGH/TOGGLE on compare match;
Microcontrollers aren't imaginable without ability to interact with other devices like indicators, input devices or other off-chip devices. For this every MCU have I/O pins that are used to interact with external world. General purpose I/O ports can be accessed via registers who provide enhanced features or simply via port registers. Port registers are allocated to the ARM bus so that fasted possible timing can be achieved. Control of individual bits is possible using single instruction. All port registers are byte and half word addressable. After MCU reset all I/O ports are set to input. Lets take LPC2000 series ARM microcontroller LPC2148. It has two 32 bit general purpose I/O ports PORT0 and PORT1. PORT0 has 30 pins for input/output operations where one is only for output. PORT1 has 16 available pins for GPIO. Each GPIO pins is controlled by four registers: IOPIN – port pin value. Depending on pin direction settings the value from this register can be read; IOSET – Writing “1” to this register sets port value to high state while writing 0 hasno effect. This register works in conjunction with IOCLR; IOCLR – This register is opposite to IOSET. Writing “1” value to it will set…
Microcontrollers aren’t imaginable without interrupts. Arm isn’t exception. In earlier articles there were SWI exceptions mentioned, but there are two more sources of exceptions: IRQ(General Purpose Interrupt) and FIQ(Tast Interrupt). ARM Pin Connect Block All I/O pins of LPC2000 ARM can be multiplexed to several functions via pin select block. Pin selection bloc allows selections up to three more other functions except GPIO. Pin Connect block give flexibility to ARM MCU because each PIN can have different functionality. After reset all pins are configured as GPIO.
Power modes especially become more important where power saving is needed. All common microcontrollers have several power control modes.LPC21xx series microcontrollers have to reduced power modes: idle and power-down mode. In idle mode execution of instructions is suspended until reset or other interrupt signal occurs. In idle mode peripheral devices (for instance timer) are running and may generate interrupts what causes processor to resume execution. So idle mode eliminates power used by processor itself, memory system, and internal buses. When power-down mode is selected, then oscillator is topped so chip doesn't receive internal clocks. After this mode is selected, all current register and memory values are preserved, all logic levels of chip remains static. Processor may be resumed by reset signal or by other external interrupt which doesn't require internal clocking (in our case it would be External interrupt). Power down mode reduces chip power consumption to nearly zero. Entering to power down mode or to idle mode is done via software, while resuming is done automatically by interrupt. Resuming is performed such way that no instructions or any data is lost. There is also possible to turn Off peripherals individually if they are not needed what allows to save…
ARM microcontrollers can be clocked im several different ways. One of the ways is to use external clock with duty cycle 50-50 and a frequency range from 1MHz to 50MHz (LPC21xx series) connected to XTAL1 pin. Other way is to connect External crystal oscillator, but its range is lower (1MHz to 30MHz for LPC21xx series). And last but not least is on-chip PLL oscillator, then external clock source frequency should not exceed range from 10MHz to 25MHz. Lets analyse more deeply each clocking mechanism. In the picture above there is fosc selection diagram shown.