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ARM7 core instruction set explained

ARM7 architecture has normal 32bit ARM7 instruction set and compressed 16 bit instruction set so called “Thumb”. ARM7 instructions has a complex behaviour. As ARM processor programming is usually written in C there is no need to be ARM expert, but understanding of basics may help in developing efficient programs.

ARM7 datatypes

ARM7 processor can support following datatypes:

  • 8 bit signed and unsigned bytes;

  • 16 bit signed and unsigned half-words;

  • 32 bit signed and unsigned words

But shorter then 32 bit datatypes are supported only by data transfer functions but when internally processed they are extended to 32 bit size. ARM7 core doesn’t support floating point datatypes – they can only be interpreted by software.

ARM memory organisation

ARM7 is capable to store words in two ways depending on weather significant byte is stored. If word MSB is stored at highest byte then operation is called “little-endian” if MSB is stored at lowest position, then it is called “big-endian”.


Usually it is easier to work with little-endian for people as they expect to be LSB at lowest position. Endian is selected in compiler settings.

ARM conditional instructions

Comparing to other RISC microcontrollers almost all ARM7 core instructions are conditionally executed. As conditional branches are standard instructions ARM instructions were extended by adding 4 bit in the top of 32 bit instruction field:


As condition field has 4 bits, there can be 16 condition values. According to condition – instruction can be executed or skipped. As we know conditions depends on N, Z, C and V flags in CPSR register. Available conditions:


Don’t use ‘NV’ as it will act as ‘nop’ operation. But it is reserved and may change in other ARM platforms. Behaviour of this is not guaranteed.

Conditional instructions are is one factor that keeps smooth program flow through pipeline. As we know when usual branch occur the pipeline is flushed and start refiling from beginning.

Practically speaking





would compile in most efficient ASM code using one conditional command.

ARM7 instruction groups

ARM7 instructions split in six main categories:

  • Branching;

  • Data processing;

  • Data transfer;

  • Block transfer;

  • Multiply;

  • Software interrupt.

Branching allows jumping forwards and backwards up to 32MB.

There are two main types of branching:

  • Branch jump with/without link exchange (link exchange means that current PC value is stored ir R14 link register);

  • Branching with/without link exchange and with instruction set exchange between ARM<->Thumb(The only recommended instruction to swap between ARM and Thumb).

Data processing includes all Logical, adding/subtracting, testing instructions (conditional/unconditional) like AND, EOR, SUB, RSB, ADD, ADC, SBC, RSC, TST, TEQ, CMP, CMN, ORR, MOV< BIC, MVN.

For instance compiler C code: if(z==1) R1=R2+(R3x4) should compile optimally to like

EQADDS R1, R2, R3, LSL #2

Data transfer instructions are used to move signed/unsigned Word, half-Word and Byte data to and from selected register. LDR and STR mnemonics.

Block transfer instructions are used to copy multiple registers with single instruction. Using LDM and STM instructions it is possible Load and Store whole register bank or subset.

Multiply instructions used for multiply operations. There are two subsets of operands MUL, MLA for 32bit results and MULL, MLAL for 64 bit results.

Software interrupt instruction SWI transfers execution to address in memory location 0x00000008 and changes mode to svc. SWI instruction can also be conditional. SWI instruction has 24 unused bits that can be used for storing data or or custom code which can be decoded in svc mode. This feature is handy in embedded OS when making operating system calls. Software interrupt will be discussed in other articles.

Wery good Reference of ARM Instructions can be downloaded from here: armref

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